74HC4017D,653, Десятичный счетчик Джонсона 16-SO
Код товара: 164685
Цена от:
18,36 руб.
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1+ 65+ 130+ 259+ 517+26,34 ₽ 23,64 ₽ 21,48 ₽ 19,68 ₽ 18,36 ₽Срок:В наличииНаличие:2 796Минимум:12Количество в заказ
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1+ 65+ 130+ 259+ 517+26,34 ₽ 23,64 ₽ 21,48 ₽ 19,68 ₽ 18,36 ₽Срок:В наличииНаличие:50Минимум:2Количество в заказ
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23+ 52+23,70 ₽ 22,98 ₽Срок:6 днейНаличие:95Минимум:Мин: 23Количество в заказ
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370+ 546+ 1095+23,82 ₽ 20,58 ₽ 20,04 ₽Срок:28 днейНаличие:2 500Минимум:Мин: 370Количество в заказ
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378+ 525+ 2000+24,72 ₽ 21,36 ₽ 20,82 ₽Срок:29 днейНаличие:2 000Минимум:Мин: 378Количество в заказ
Описание 74HC4017D,653
The 74HC4017D is a 5-stage Johnson Decade Counter with 10 decoded outputs (Q0 to Q9), an output from the most significant flip-flop (Q5\-9), two clock inputs (CP0 and CP1\) and an overriding asynchronous master reset input (MR). The counter is advanced by either a low-to-high transition at CP0 while CP1\ is low or a high-to-low transition at CP1\ while CP0 is high. When cascading counters, the Q5\-9 output, which is low while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter. A high on MR resets the counter to zero (Q0 = Q5\-9 = high, Q1 to Q9 = low) independent of the clock inputs (CP0 and CP1\). Automatic code correction of the counter is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
• CMOS Input level
• Complies with JEDEC standard No. 7A
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